Discussion:
[Freetel-codec2] SM1000 and the FreeDV 700B mode
Stuart Longland
2015-10-25 00:01:36 UTC
Permalink
Hi all,

I'm now starting to look at the 700B mode, since that would be the next
major advance for the SM1000. (All the little stuff that can be
practically achieved has been achieved.)

I put this off until I got a better understanding of how the code
worked. As I understand it, the structures for FreeDV are allocated on
the heap using malloc, and that to switch modes, I must first free the
existing instance and open a new one.
/* Set up FreeDV modem */
f = freedv_open(FREEDV_MODE_700B);
n_samples = freedv_get_n_speech_samples(f);
n_samples_16k = 2*n_samples;
short adc16k[FDMDV_OS_TAPS_16K+n_samples_16k];
short dac16k[n_samples_16k];
short adc8k[n_samples];
short dac8k[FDMDV_OS_TAPS_8K+n_samples];
The n_samples bit concerns me though. That basically decides the size
of the buffers used in encoding/decoding.

Interestingly, we seem to be passing an integer non-const variable in
the declaration of these arrays; didn't think that was allowed. (It
clearly is here, then again, I've seen some like the TI Code Composer
compiler which would definitely reject that bit of code.)

These arrays get declared on the stack, so are going to be hard to
change. We can pretend they are smaller, but not bigger.

To my way of thinking, we have a couple of options:
1. We can use malloc/free to allocate these on the heap, which means we
can re-allocate them later.
2. We can pick a size that will be big enough for both 700B and 1600,
and leave them fixed at that size.
3. We allocate two sets of buffers, one for 700B, the other for 1600.

Option 3 seems unwieldy in terms of code footprint and memory usage, so
probably not worth considering.

Option 2 would be the simplest, but I have no idea how big n_samples is,
or how much it changes.

Option 1 wouldn't be too hard, but I'm not sure what the implementation
of malloc/free permits. Some embedded versions have funny restrictions
like requiring you to free objects in the reverse order to their
allocations. Some don't actually implement free().

Then there's the game of dealing with memory fragmentation. Each of
those could bite us in unexpected ways.

The other option is we just forgo giving the user a choice at run-time.
The device stores the 700B/1600 mode selection in its configuration
settings, and to change it requires a power-cycle to reboot.

What's actually needed in order to switch from one mode to the other?
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
Stuart Longland
2015-10-25 00:06:40 UTC
Permalink
/* Set up FreeDV modem */
f = freedv_open(FREEDV_MODE_700B);
Hmm, and even just having it do 700B alone, more to it is needed than
just this.

Changing 1600 to 700B causes the SM1000 to crap itself when going into
DV receive mode.
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
Brady O'Brien
2015-10-25 00:25:44 UTC
Permalink
I haven't looked at the 700b code, but I think it is not yet optimized for
the memory of the stm32f4. I'd start by writing a little unit test or
something to see what it's using on the PC and going from there.

David's process of porting 1600 over is detailed here:
http://www.rowetel.com/blog/?p=3427

Keep up the good work!
Post by Stuart Longland
/* Set up FreeDV modem */
f = freedv_open(FREEDV_MODE_700B);
Hmm, and even just having it do 700B alone, more to it is needed than
just this.
Changing 1600 to 700B causes the SM1000 to crap itself when going into
DV receive mode.
--
Stuart Longland (aka Redhatter, VK4MSL)
I haven't lost my mind...
...it's backed up on a tape somewhere.
------------------------------------------------------------------------------
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David Rowe
2015-10-25 00:27:02 UTC
Permalink
Hi Stuart,

1/ Nice work on the UI improvements. I'd be happy to work with you on
an option where we can use compressed speech prompts (my morse is rusty!).

2/ FB on taking a look at 700B mode. I described some suggested first
steps on an email to the list on 24 Sep. Happy to work with you based
on the results of these unit tests. I imagine I'll be up for some modem
memory/CPU optimisation.

Cheers,

David
Post by Stuart Longland
/* Set up FreeDV modem */
f = freedv_open(FREEDV_MODE_700B);
Hmm, and even just having it do 700B alone, more to it is needed than
just this.
Changing 1600 to 700B causes the SM1000 to crap itself when going into
DV receive mode.
------------------------------------------------------------------------------
Stuart Longland
2015-10-25 00:44:52 UTC
Permalink
Hi David,
Post by David Rowe
1/ Nice work on the UI improvements. I'd be happy to work with you on
an option where we can use compressed speech prompts (my morse is rusty!).
Yep, that would definitely be worth doing.

Having gotten the time-out timer working, I'll probably have to put this
aside for a bit and go get some chores done for the week.

Then I might start looking at what's needed since that would be the next
easiest option.
Post by David Rowe
2/ FB on taking a look at 700B mode. I described some suggested first
steps on an email to the list on 24 Sep. Happy to work with you based
on the results of these unit tests. I imagine I'll be up for some modem
memory/CPU optimisation.
Yep, I did see that. I'm looking around for a suitable debugger board,
as it's impossible to see what's going on right now. All I have is some
STM32F103 boards (Cortex M3; 64kB RAM, 512kB flash, no FPU) and the
SM1000 which has no JTAG exposed.

The STLink/V2 programmer cables are not expensive and OpenOCD supports
them. Might be time to let some moths out of the wallet. ;-)

Regards,
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
David Rowe
2015-10-25 01:39:19 UTC
Permalink
Hi Stuart,

Re debugger suggest a $20 STM32F4 Discovery. It has a debugger uC and a
STM32F4 on board. Standalone (without the SM1000) it can run STM32F4
unit tests, using stdio.h functions to/from a Host PC (semi-hosting)

You can then move a few jumpers and attach it to the SM1000 as a ST-LINK
debugger/flasher, see SM1000 page "Testing and Debugging" section for links.

However TBH I avoid any actual "debugging" with gdb on the STM32F4. I
get the modules working on a PC first then run unit tests on the STM32F4
using semi-hosting to track down any differences.

Cheers,

David
Post by Stuart Longland
Hi David,
Post by David Rowe
1/ Nice work on the UI improvements. I'd be happy to work with you on
an option where we can use compressed speech prompts (my morse is rusty!).
Yep, that would definitely be worth doing.
Having gotten the time-out timer working, I'll probably have to put this
aside for a bit and go get some chores done for the week.
Then I might start looking at what's needed since that would be the next
easiest option.
Post by David Rowe
2/ FB on taking a look at 700B mode. I described some suggested first
steps on an email to the list on 24 Sep. Happy to work with you based
on the results of these unit tests. I imagine I'll be up for some modem
memory/CPU optimisation.
Yep, I did see that. I'm looking around for a suitable debugger board,
as it's impossible to see what's going on right now. All I have is some
STM32F103 boards (Cortex M3; 64kB RAM, 512kB flash, no FPU) and the
SM1000 which has no JTAG exposed.
The STLink/V2 programmer cables are not expensive and OpenOCD supports
them. Might be time to let some moths out of the wallet. ;-)
Regards,
------------------------------------------------------------------------------
Stuart Longland
2015-10-25 08:38:19 UTC
Permalink
Hi David,
Post by David Rowe
Re debugger suggest a $20 STM32F4 Discovery. It has a debugger uC and a
STM32F4 on board. Standalone (without the SM1000) it can run STM32F4
unit tests, using stdio.h functions to/from a Host PC (semi-hosting)
You can then move a few jumpers and attach it to the SM1000 as a ST-LINK
debugger/flasher, see SM1000 page "Testing and Debugging" section for links.
Yes, this is an option too. Neither is a particularly expensive option.
Post by David Rowe
However TBH I avoid any actual "debugging" with gdb on the STM32F4. I
get the modules working on a PC first then run unit tests on the STM32F4
using semi-hosting to track down any differences.
Yeah, in the case of tracking down FreeDV 700B though, it might be
useful to single-step it until things go pear shaped, although after
stumbling on some #ifdef's, I have an idea what might be going on.

In the meantime, I'm starting to get together some speech playback
goodness. The first step is figuring out how to represent the phrases,
so that our voice-over person doesn't have to record separate recordings
for every permutation of setting and value.

This is being done in a branch for now.
http://git.longlandclan.id.au/?p=for-upstream/freedv/codec2.git;a=commit;h=61287ddb5a5e421e3a9b2da49aba7cfba102d2e5

The thought is, the phrases will be simple structs that either encode a
length of silence, a run of digits/letters, or point to a Codec2
recording. When I've deduced a recording, I track the frame number,
feeding the decoder with frames and upsampling the samples at the other end.

Hopefully it won't hurt the CPU too much.

Regards,
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
glen english
2015-10-25 08:43:23 UTC
Permalink
On the large micros like STMF4, for fast development/ compile run cycles
I run my entire executable out of RAM.... only transitioning to flash
when I have to disconnect the debugger.

Optimized DSP code from the CMSDSP libraries (which I re compile)
certainly takes a performance hit, but not too badly.

If you are not already using the optimized , ST hand coded in assembler
DSP libraries, I'd be surprised if anyone could do better.

g
Post by Stuart Longland
Hi David,
Post by David Rowe
Re debugger suggest a $20 STM32F4 Discovery. It has a debugger uC and a
STM32F4 on board. Standalone (without the SM1000) it can run STM32F4
unit tests, using stdio.h functions to/from a Ho
------------------------------------------------------------------------------
David Rowe
2015-10-25 19:11:17 UTC
Permalink
I recall reading about an option to run from RAM, however we only have
128k+96k or RAM and the code already 500k. Flashing takes a few seconds
so I've never really noticed it.

I use software engineering practices (as per my email on 24 Sep) that
mean 99% of my debugging is done before the code gets near the SMT32F4
target. You don't want to be sorting out DSP bugs on a bare metal platform.

Haven't found a use for the CMSDSP libs to date. If we did use them
we'd also need them on the PC side to ensure identical behavior. Some
high level optimisation of the C code has been enough so far.

Been many years since I did any DSP assembler. Getting away from that
is the whole idea of using a modern, powerful uC. Same code runs on
your PC as your uC.

- David
Post by glen english
On the large micros like STMF4, for fast development/ compile run cycles
I run my entire executable out of RAM.... only transitioning to flash
when I have to disconnect the debugger.
Optimized DSP code from the CMSDSP libraries (which I re compile)
certainly takes a performance hit, but not too badly.
If you are not already using the optimized , ST hand coded in assembler
DSP libraries, I'd be surprised if anyone could do better.
g
Post by Stuart Longland
Hi David,
Post by David Rowe
Re debugger suggest a $20 STM32F4 Discovery. It has a debugger uC and a
STM32F4 on board. Standalone (without the SM1000) it can run STM32F4
unit tests, using stdio.h functions to/from a Ho
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
glen english
2015-10-25 22:28:46 UTC
Permalink
yeah if the code is out at 500k . golly ! no way it's gonna run in RAM !

The DSP libs are worth a look if you get stuck for MFLOPS.

cheers
Post by David Rowe
I recall reading about an option to run from RAM, however we only have
128k+96k or RAM and the code already 500k. Flashing takes a few seconds
so I've never really noticed it.
I use software engineering practices (as per my email on 24 Sep) that
mean 99% of my debugging is done before the code gets near the SMT32F4
target. You don't want to be sorting out DSP bugs on a bare metal platform.
Haven't found a use for the CMSDSP libs to date. If we did use them
we'd also need them on the PC side to ensure identical behavior. Some
high level optimisation of the C code has been enough so far.
Been many years since I did any DSP assembler. Getting away from that
is the whole idea of using a modern, powerful uC. Same code runs on
your PC as your uC.
- David
Post by glen english
On the large micros like STMF4, for fast development/ compile run cycles
I run my entire executable out of RAM.... only transitioning to flash
when I have to disconnect the debugger.
Optimized DSP code from the CMSDSP libraries (which I re compile)
certainly takes a performance hit, but not too badly.
If you are not already using the optimized , ST hand coded in assembler
DSP libraries, I'd be surprised if anyone could do better.
g
Post by Stuart Longland
Hi David,
Post by David Rowe
Re debugger suggest a $20 STM32F4 Discovery. It has a debugger uC and a
STM32F4 on board. Standalone (without the SM1000) it can run STM32F4
unit tests, using stdio.h functions to/from a Ho
------------------------------------------------------------------------------
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Freetel-codec2 mailing list
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------------------------------------------------------------------------------
_______________________________________________
Freetel-codec2 mailing list
https://lists.sourceforge.net/lists/listinfo/freetel-codec2
--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
David Rowe
2015-10-27 19:47:17 UTC
Permalink
Hello Glen/Matt,

I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?

For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.

Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.

I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.

Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.

Thanks,

David

------------------------------------------------------------------------------
Helmut
2015-10-27 22:22:38 UTC
Permalink
Hi David,

just my 2 cts. You will find in each datasheet of ADCs for RF apps the
typical parameters SNR, SFDR, ENOB, max. sampling rate and bandwidth. The
knowledge of these values, mostly relating to full scale and the Nyquist
bandwidth, are sufficient to define a frontend including the necessary
preamp, filtering and matching ADC to 50 ohms 'function blocks'. Together
with your channel bandwidth you can provide a reliable estimation of MDS and
dynamic range of the radio (my favorite direct sampling technique assumed,
hi). It's good choice to calculate with a figure of about 50 dB for the ADC.

Walt Kester of AD wrote a couple of nice tutorials, e.g.
http://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: David Rowe [mailto:***@rowetel.com]
Gesendet: Dienstag, 27. Oktober 2015 20:47
An: freetel-***@lists.sourceforge.net
Betreff: [Freetel-codec2] gain before ADC

Hello Glen/Matt,

I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?

For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.

Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.

I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.

Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.

Thanks,

David

----------------------------------------------------------------------------
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------------------------------------------------------------------------------
glen english
2015-10-28 06:33:24 UTC
Permalink
Howdy
A good response Helmut

The oversampling ratio (OSR) , clock purity will dominate.

What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.

With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !

With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.

The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.

IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .

For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.

The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm

so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....

In my experience the SFDR is what will limit the sensitivity.

Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)

NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)

The noise figure of the converter is approx (the input level - the SNR)
- 174

IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.


cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
_______________________________________________
Freetel-codec2 mailing list
https://lists.sourceforge.net/lists/listinfo/freetel-codec2
--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
David Rowe
2015-10-28 21:00:16 UTC
Permalink
Thank you Helmut, Glen, and Steve,

1/ Ok it's starting to make sense, lets see if I can work through a
contrived example:

We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
is 1Vrms (10dBm). It samples at 48 kHz:

The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.

Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.

2/ I'm actually working on narrow band constant envelope radio, So:

BPF- LNA - Mixer - Xtal filter - limiting amp - ADC

If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?

Thanks,

David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
Helmut
2015-10-28 22:29:21 UTC
Permalink
Hi David,

I understood what you plan, but analogue down conversion is another story.
The example I sent you should demonstrate how this attached system
calculation tool works. It shows a VHF frontend for digital down conversion,
i.e. the ADC has to be sampled with 300 Msps. The BPF of 144 to 146 MHz
exhibits an insertion loss of 2 dB in the stop band and consequently a noise
figure of 2 dB.
In your case NF or MDS is mainly not determined by the ADC in the base band,
but on all analogue stages in front. It depends e.g. on what kind of mixer
you intend to use: balanced passive mixers exhibit an insertion loss of 7-8
dB (equal NF 7- 8 dB), while modern active mixer provide even conversion
gain. BTW negative NF doesn’t exist. I guess you meant negative gain (loss)
of the BPF.
Nevertheless you can use that SYScal tool of course also for your approach
to calculate the necessary gain of preamp and IF amp.


73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: David Rowe [mailto:***@rowetel.com]
Gesendet: Mittwoch, 28. Oktober 2015 22:00
An: freetel-***@lists.sourceforge.net
Betreff: Re: [Freetel-codec2] gain before ADC

Thank you Helmut, Glen, and Steve,

1/ Ok it's starting to make sense, lets see if I can work through a
contrived example:

We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
is 1Vrms (10dBm). It samples at 48 kHz:

The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.

Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.

2/ I'm actually working on narrow band constant envelope radio, So:

BPF- LNA - Mixer - Xtal filter - limiting amp - ADC

If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?

Thanks,

David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
----------------------------------------------------------------------------
--
Post by glen english
Post by David Rowe
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----------------------------------------------------------------------------
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_______________________________________________
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Freetel-***@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/freetel-codec2


------------------------------------------------------------------------------
Matthew Cook
2015-10-28 23:42:38 UTC
Permalink
David,

Ok that's just a straight direct conversion receiver. As Helmut has said
this is a different beast. The majority of your design decisions will be
made in the analogue world.

Here's a few good worked examples for you to look at, it doesn't matter
these are for HF the same rule applies you just need too substitute for the
components you can source at your frequency of interest.

http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qst/1993/02/page23/
http://www.arrl.org/files/file/QEX_Next_Issue/Jul-Aug_2013/QEX_7_13_Horrabin.pdf

Somewhere I've got a copy of Doug DeMaw (W1FB) receiver design book, I must
try to find it and let you have a read. Dougs book discusses the trade
off's moving amps and filters around the mixer etc.

Oh and with your ring diode mixer, look at putting a diplexer in there to
terminate all the unwanted energy in a resistor and pick off the band of
interest before feeding to your post mixer amp. Lots of references on the
net for doing this.

73

Matthew
VK5ZM
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance
capability.
Post by glen english
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would
help.
Post by glen english
Post by David Rowe
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
Post by glen english
Post by David Rowe
_______________________________________________
Freetel-codec2 mailing list
https://lists.sourceforge.net/lists/listinfo/freetel-codec2
------------------------------------------------------------------------------
_______________________________________________
Freetel-codec2 mailing list
https://lists.sourceforge.net/lists/listinfo/freetel-codec2
glen english
2015-10-29 00:00:19 UTC
Permalink
------------------------------------------------------------------------------
Matthew Cook
2015-10-29 00:04:48 UTC
Permalink
Hmm... Good point Crystal filter should have given it away. I need more
coffee or glasses one of the two.

73

Matthew
VK5ZM
Not direct conversion Matthew- that is a superhet- David will undersample
the IF.
David,
Ok that's just a straight direct conversion receiver. As Helmut has said
this is a different beast. The majority of your design decisions will be
made in the analogue world.
Here's a few good worked examples for you to look at, it doesn't matter
these are for HF the same rule applies you just need too substitute for the
components you can source at your frequency of interest.
http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qst/1993/02/page23/
http://www.arrl.org/files/file/QEX_Next_Issue/Jul-Aug_2013/QEX_7_13_Horrabin.pdf
Somewhere I've got a copy of Doug DeMaw (W1FB) receiver design book, I
must try to find it and let you have a read. Dougs book discusses the
trade off's moving amps and filters around the mixer etc.
Oh and with your ring diode mixer, look at putting a diplexer in there to
terminate all the unwanted energy in a resistor and pick off the band of
interest before feeding to your post mixer amp. Lots of references on the
net for doing this.
73
Matthew
VK5ZM
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance
capability.
Post by glen english
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a
3Vpp
Post by glen english
Post by David Rowe
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would
help.
Post by glen english
Post by David Rowe
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
Post by glen english
Post by David Rowe
_______________________________________________
Freetel-codec2 mailing list
https://lists.sourceforge.net/lists/listinfo/freetel-codec2
------------------------------------------------------------------------------
_______________________________________________
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https://lists.sourceforge.net/lists/listinfo/freetel-codec2
------------------------------------------------------------------------------
_______________________________________________
--
-
Glen English
RF Communications and Electronics Engineer
CORTEX RF
&
Pacific Media Technologies Pty Ltd
ABN 40 075 532 008
PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077
------------------------------------------------------------------------------
_______________________________________________
Freetel-codec2 mailing list
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glen english
2015-10-29 01:38:25 UTC
Permalink
Crystal filter is legit- could have been at fundamental...
IE you can get a crystal filter for 147.0000 MHz/
but

MIXER gives it away...

cheers
Post by Matthew Cook
Hmm... Good point Crystal filter should have given it away. I need
more coffee or glasses one of the two.
73
Matthew
VK5ZM
------------------------------------------------------------------------------
Stephen Hicks, N5AC
2015-10-29 00:04:46 UTC
Permalink
David for your analog stages, you should do an Internet search for cascaded
noise figure. This will show you how to run the calculations around NF and
Gain. Alternately you can use a tool such as Agilent/HP's AppCAD
software. Search for "appcad woodshot" and it will be the first link. You
ACD will be the last stage in the equation with the NF you have already
calculated. You will be able to see how different preamps and other
components will affect the system noise figure.

Steve


Stephen Hicks, N5AC
VP Engineering
FlexRadio Systems™
4616 W Howard Ln Ste 1-150
Austin, TX 78728
Phone: 512-535-4713 x205
Email: ***@flexradio.com
Web: www.flexradio.com
Click Here for PGP Public Key
<https://sites.google.com/a/flex-radio.com/pgp-public-keys/n5ac>



*Tune In Excitement™*
PowerSDR™ is a trademark of FlexRadio Systems
Not direct conversion Matthew- that is a superhet- David will undersample
the IF.
David,
Ok that's just a straight direct conversion receiver. As Helmut has said
this is a different beast. The majority of your design decisions will be
made in the analogue world.
Here's a few good worked examples for you to look at, it doesn't matter
these are for HF the same rule applies you just need too substitute for the
components you can source at your frequency of interest.
http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qst/1993/02/page23/
http://www.arrl.org/files/file/QEX_Next_Issue/Jul-Aug_2013/QEX_7_13_Horrabin.pdf
Somewhere I've got a copy of Doug DeMaw (W1FB) receiver design book, I
must try to find it and let you have a read. Dougs book discusses the
trade off's moving amps and filters around the mixer etc.
Oh and with your ring diode mixer, look at putting a diplexer in there to
terminate all the unwanted energy in a resistor and pick off the band of
interest before feeding to your post mixer amp. Lots of references on the
net for doing this.
73
Matthew
VK5ZM
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance
capability.
Post by glen english
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a
3Vpp
Post by glen english
Post by David Rowe
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would
help.
Post by glen english
Post by David Rowe
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
Post by glen english
Post by David Rowe
_______________________________________________
Freetel-codec2 mailing list
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------------------------------------------------------------------------------
_______________________________________________
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https://lists.sourceforge.net/lists/listinfo/freetel-codec2
------------------------------------------------------------------------------
_______________________________________________
--
-
Glen English
RF Communications and Electronics Engineer
CORTEX RF
&
Pacific Media Technologies Pty Ltd
ABN 40 075 532 008
PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077
------------------------------------------------------------------------------
_______________________________________________
Freetel-codec2 mailing list
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glen english
2015-10-28 23:58:54 UTC
Permalink
Hi David
Glad my description of NF made sense.

If your limiter is perfectly doing its job, then yes 1 bit is all you need.

I like seeing the xtal filter in there ! This reduces the umming and
ahhhing by two to three orders of magnitude.

Of course the filter stop-bands are finite, so you must consider this, also.

I'm guessing you are going to undersample. Goes without saying that ADC
performance degrades quickly on super nyquist but this is unlikely to be
any issue in this design.

Final sample rate needs to be at least two times the IF filter BW, 4x if
you want to not make life hell for your digital filters.

My guess is, you could use a single pin of the STM32 inconjunction with
some timer and input compare block to get a very nice and periodic 1
bit sampler.

Dont expect miracles though. Analog limiters are dreadful things. if you
want some REALLY good limiter lessons tuition , go look at the FM
limiter in a analog VIDEO CASSETTE RECORDER. They are the very best,
high bandwidth (10 MHz) limiters around....

For a IF width of 15kHz, I'd suggest a SR of about 60 k. ( an enormous
undersample) ..That will help also preventing strong adjacent channels
aliasing.

regards
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
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------------------------------------------------------------------------------
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https://lists.sourceforge.net/lists/listinfo/freetel-codec2
--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
David Rowe
2015-10-29 01:31:19 UTC
Permalink
Hi Guys,

Thanks again for all your tips and insight. I'm following up yr
references and doing lots of reading.

Glen - I haven't decided if I'll undersample yet or use a 2nd mixer from
10.7MHz to low IF.

Steve - I have built up a spreadsheet to work out cascaded NF, MDS, and
ADC NF. Am working through each calculation step nice and slowly! Also
prototyping some of this and getting results a few dB from my
calculations which is encouraging.

Matt I'm using a termination insensitive amp at the mixer IF port, have
measured it's return loss as 20dB between 10.7MHz and 300MHz (2LO is
272MHz).

Glen - what problems should I look out for with a limiting amp? Any
tests I can do to spot issues early? I guess two-tone wouldn't work.

Cheers,

David
Post by Stuart Longland
Hi David
Glad my description of NF made sense.
If your limiter is perfectly doing its job, then yes 1 bit is all you need.
I like seeing the xtal filter in there ! This reduces the umming and
ahhhing by two to three orders of magnitude.
Of course the filter stop-bands are finite, so you must consider this, also.
I'm guessing you are going to undersample. Goes without saying that ADC
performance degrades quickly on super nyquist but this is unlikely to be
any issue in this design.
Final sample rate needs to be at least two times the IF filter BW, 4x if
you want to not make life hell for your digital filters.
My guess is, you could use a single pin of the STM32 inconjunction with
some timer and input compare block to get a very nice and periodic 1
bit sampler.
Dont expect miracles though. Analog limiters are dreadful things. if you
want some REALLY good limiter lessons tuition , go look at the FM
limiter in a analog VIDEO CASSETTE RECORDER. They are the very best,
high bandwidth (10 MHz) limiters around....
For a IF width of 15kHz, I'd suggest a SR of about 60 k. ( an enormous
undersample) ..That will help also preventing strong adjacent channels
aliasing.
regards
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
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------------------------------------------------------------------------------
glen english
2015-10-29 01:40:49 UTC
Permalink
put AM through it and see how much you get out... that is a limiter
test.....

I use the analog devices tool ADI sim RF. excellent.

I think worrying about mixer terminations is important but you have
bigger fish to fry yet.

Try ADL5350 for a mixer.watch spurious products.

g
Post by David Rowe
Hi Guys,
Thanks again for all your tips and insight. I'm following up yr
references and doing lots of reading.
Glen - I haven't decided if I'll undersample yet or use a 2nd mixer from
10.7MHz to low IF.
Steve - I have built up a spreadsheet to work out cascaded NF, MDS, and
ADC NF. Am working through each calculation step nice and slowly! Also
prototyping some of this and getting results a few dB from my
calculations which is encouraging.
Matt I'm using a termination insensitive amp at the mixer IF port, have
measured it's return loss as 20dB between 10.7MHz and 300MHz (2LO is
272MHz).
Glen - what problems should I look out for with a limiting amp? Any
tests I can do to spot issues early? I guess two-tone wouldn't work.
Cheers,
David
Post by Stuart Longland
Hi David
Glad my description of NF made sense.
If your limiter is perfectly doing its job, then yes 1 bit is all you need.
I like seeing the xtal filter in there ! This reduces the umming and
ahhhing by two to three orders of magnitude.
Of course the filter stop-bands are finite, so you must consider this, also.
I'm guessing you are going to undersample. Goes without saying that ADC
performance degrades quickly on super nyquist but this is unlikely to be
any issue in this design.
Final sample rate needs to be at least two times the IF filter BW, 4x if
you want to not make life hell for your digital filters.
My guess is, you could use a single pin of the STM32 inconjunction with
some timer and input compare block to get a very nice and periodic 1
bit sampler.
Dont expect miracles though. Analog limiters are dreadful things. if you
want some REALLY good limiter lessons tuition , go look at the FM
limiter in a analog VIDEO CASSETTE RECORDER. They are the very best,
high bandwidth (10 MHz) limiters around....
For a IF width of 15kHz, I'd suggest a SR of about 60 k. ( an enormous
undersample) ..That will help also preventing strong adjacent channels
aliasing.
regards
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance capability.
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone intermods
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always 12-96
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
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--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
Matthew Cook
2015-10-29 04:56:36 UTC
Permalink
David,

If you're going to use a diode mixer then terminating *is* important, for
your amusement/reading;

http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qex/2001/05_06/page45/index.html

There are termination insensitive mixers to go with your termination
insensitive amplifier;

https://www.miteq.com/docs/MITEQ_Mixers_TermInsensitve.pdf

But they cost a lot and don't really get you that much further than say
terminating your mixer in a -6dB pad and living with the additional
conversion loss.

The mixer that Glen suggests is a nice unit with great specs, that sounds
like a serious leg up to me.

Also watch those IP3's from end to end.

73

Matthew
VK5ZM
Post by David Rowe
Hi Guys,
Thanks again for all your tips and insight. I'm following up yr
references and doing lots of reading.
Glen - I haven't decided if I'll undersample yet or use a 2nd mixer from
10.7MHz to low IF.
Steve - I have built up a spreadsheet to work out cascaded NF, MDS, and
ADC NF. Am working through each calculation step nice and slowly! Also
prototyping some of this and getting results a few dB from my
calculations which is encouraging.
Matt I'm using a termination insensitive amp at the mixer IF port, have
measured it's return loss as 20dB between 10.7MHz and 300MHz (2LO is
272MHz).
Glen - what problems should I look out for with a limiting amp? Any
tests I can do to spot issues early? I guess two-tone wouldn't work.
Cheers,
David
Post by Stuart Longland
Hi David
Glad my description of NF made sense.
If your limiter is perfectly doing its job, then yes 1 bit is all you
need.
Post by Stuart Longland
I like seeing the xtal filter in there ! This reduces the umming and
ahhhing by two to three orders of magnitude.
Of course the filter stop-bands are finite, so you must consider this,
also.
Post by Stuart Longland
I'm guessing you are going to undersample. Goes without saying that ADC
performance degrades quickly on super nyquist but this is unlikely to be
any issue in this design.
Final sample rate needs to be at least two times the IF filter BW, 4x if
you want to not make life hell for your digital filters.
My guess is, you could use a single pin of the STM32 inconjunction with
some timer and input compare block to get a very nice and periodic 1
bit sampler.
Dont expect miracles though. Analog limiters are dreadful things. if you
want some REALLY good limiter lessons tuition , go look at the FM
limiter in a analog VIDEO CASSETTE RECORDER. They are the very best,
high bandwidth (10 MHz) limiters around....
For a IF width of 15kHz, I'd suggest a SR of about 60 k. ( an enormous
undersample) ..That will help also preventing strong adjacent channels
aliasing.
regards
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB. Its FSD
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is -86-10*log10(24E3) =
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC NF is
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a negative NF -
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK), what are
the SNR/SFDR requirements for the ADC? The limiting amp has removed all
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm (roughly
what you have) , and 60dB of SNR will put your noise floor at 12-60 =
-48dBm, so you'll need 72dB of gain. And so it will overload on the
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on. I know
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be all sorts
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance
capability.
Post by Stuart Longland
Post by David Rowe
Post by glen english
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not change,
the SFDR is still 60dB. So you can improve dynamic range, but not the
SFDR. The SFDR, or more likely, where the third order two tone
intermods
Post by Stuart Longland
Post by David Rowe
Post by glen english
are, won't change. Some LT converters have incredibly good SFDRs via
internal digital dithering (later subtracted out in your receiver) .
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be always
12-96
Post by Stuart Longland
Post by David Rowe
Post by glen english
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in front of
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter is also
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO important
that the convertor is seeing a low pass (nyquist) or band pass filter
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level - the SNR)
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my open
source
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a
3Vpp
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB
above
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example
would help.
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
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Post by Stuart Longland
Post by David Rowe
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glen english
2015-10-29 06:32:10 UTC
Permalink
------------------------------------------------------------------------------
David Rowe
2015-10-29 19:12:41 UTC
Permalink
Hi Matt,

The Termination Insensitive Amplifier is a transistor circuit that uses
feedback to present 50 ohms to the mixer IF port across a wide range of
frequencies.

I've measured the return loss (i.e. match compared to a pure 50 ohm
resistive load) of the input port of the TIA to be about 20dB between
the IF frequency and twice the LO freq.

All - a little about the philosophy and aims of this project:

I'm not shooting for high end RF performance, e.g. contest grade IP3,
low phase noise, high ACR, high tx power, multi-band operation. There
are others who can do that much better than I.

Rather, I want to use this radio to demonstrate advanced new VHF DV
ideas, for example:

i) completely open source (hardware, software, codec, modem, protocol
stack) VHF DV.
ii) Diplexor free TDMA repeaters on low cost hardware
iii) variable bit rate/quality speech codecs
iv) Diversity rx to address fading
v) a 10dB gain over analog FM and current, 1st gen VHF DV systems

(i) to (v) break a lot of new ground, and are "enough" for any one
project. To demonstrate them I feel I need a custom radio: for example
TDMA timing means we need control by a bare metal uC (no operating
system) to get the timing right. I also need an up-conversion/SDR tx
rather than direct FM to make sure the modem is done right.

Cheers,

David
Post by Stuart Longland
David,
If you're going to use a diode mixer then terminating _is_ important,
for your amusement/reading;
http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qex/2001/05_06/page45/index.html
There are termination insensitive mixers to go with your termination
insensitive amplifier;
https://www.miteq.com/docs/MITEQ_Mixers_TermInsensitve.pdf
But they cost a lot and don't really get you that much further than say
terminating your mixer in a -6dB pad and living with the additional
conversion loss.
The mixer that Glen suggests is a nice unit with great specs, that
sounds like a serious leg up to me.
Also watch those IP3's from end to end.
73
Matthew
VK5ZM
Hi Guys,
Thanks again for all your tips and insight. I'm following up yr
references and doing lots of reading.
Glen - I haven't decided if I'll undersample yet or use a 2nd mixer from
10.7MHz to low IF.
Steve - I have built up a spreadsheet to work out cascaded NF, MDS, and
ADC NF. Am working through each calculation step nice and slowly! Also
prototyping some of this and getting results a few dB from my
calculations which is encouraging.
Matt I'm using a termination insensitive amp at the mixer IF port, have
measured it's return loss as 20dB between 10.7MHz and 300MHz (2LO is
272MHz).
Glen - what problems should I look out for with a limiting amp? Any
tests I can do to spot issues early? I guess two-tone wouldn't work.
Cheers,
David
Post by Stuart Longland
Hi David
Glad my description of NF made sense.
If your limiter is perfectly doing its job, then yes 1 bit is
all you need.
Post by Stuart Longland
I like seeing the xtal filter in there ! This reduces the umming and
ahhhing by two to three orders of magnitude.
Of course the filter stop-bands are finite, so you must consider
this, also.
Post by Stuart Longland
I'm guessing you are going to undersample. Goes without saying
that ADC
Post by Stuart Longland
performance degrades quickly on super nyquist but this is
unlikely to be
Post by Stuart Longland
any issue in this design.
Final sample rate needs to be at least two times the IF filter
BW, 4x if
Post by Stuart Longland
you want to not make life hell for your digital filters.
My guess is, you could use a single pin of the STM32
inconjunction with
Post by Stuart Longland
some timer and input compare block to get a very nice and
periodic 1
Post by Stuart Longland
bit sampler.
Dont expect miracles though. Analog limiters are dreadful things.
if you
Post by Stuart Longland
want some REALLY good limiter lessons tuition , go look at the FM
limiter in a analog VIDEO CASSETTE RECORDER. They are the very best,
high bandwidth (10 MHz) limiters around....
For a IF width of 15kHz, I'd suggest a SR of about 60 k. ( an
enormous
Post by Stuart Longland
undersample) ..That will help also preventing strong adjacent
channels
Post by Stuart Longland
aliasing.
regards
Post by David Rowe
Thank you Helmut, Glen, and Steve,
1/ Ok it's starting to make sense, lets see if I can work through a
We have a 16 bit sound blaster ADC, with a SNR of 6*15 = 90dB.
Its FSD
Post by Stuart Longland
Post by David Rowe
The ADC noise floor is at 10-96=-86dBm. This is in a Nyquist BW of
48kHz, so the noise power normalised to a 1Hz BW is
-86-10*log10(24E3) =
Post by Stuart Longland
Post by David Rowe
-129.8dBm/Hz. The thermal noise floor is -174dBm/Hz so our ADC
NF is
Post by Stuart Longland
Post by David Rowe
174-129.8 = 44.2dB.
Help me understand what NF is too, and why a filter has a
negative NF -
Post by Stuart Longland
Post by David Rowe
it moves the signal closer to the thermal noise floor.
BPF- LNA - Mixer - Xtal filter - limiting amp - ADC
If I am sampling a constant envelope signal (FM, FSK, GMSK),
what are
Post by Stuart Longland
Post by David Rowe
the SNR/SFDR requirements for the ADC? The limiting amp has
removed all
Post by Stuart Longland
Post by David Rowe
amplitude information. So do we just need the sign bit of the ADC?
Could we just sample the signal with a flip flop?
Thanks,
David
Post by glen english
Howdy
A good response Helmut
The oversampling ratio (OSR) , clock purity will dominate.
What is your planned OSR , and sampler rate ?
quadruple the sample rate , gain a bit of ADC of course.
With an OSR = 1, for -120dBm , and full scale of say +12dBm
(roughly
Post by Stuart Longland
Post by David Rowe
Post by glen english
what you have) , and 60dB of SNR will put your noise floor at
12-60 =
Post by Stuart Longland
Post by David Rowe
Post by glen english
-48dBm, so you'll need 72dB of gain. And so it will overload
on the
Post by Stuart Longland
Post by David Rowe
Post by glen english
slightest thing out there !
With an OSR of 4x, you are 6dB or 1 bit better off, and so on.
I know
Post by Stuart Longland
Post by David Rowe
Post by glen english
you understand this stuff so I wont elaborate.
The SFDR of the converter will dominate what it can USEFULLY hear,
because below the SFDR , REGARDLESS of the OSR, there will be
all sorts
Post by Stuart Longland
Post by David Rowe
Post by glen english
of funny converter artifacts, and the intermods will be there also.
So the SFDR , not the OSR ultimately determines the performance
capability.
Post by Stuart Longland
Post by David Rowe
Post by glen english
IE the SNR might be 60dB, say a 10 bit converter,
if the OSR = 4 then you'll get 66dB SNR, BUTthe SFDR does not
change,
Post by Stuart Longland
Post by David Rowe
Post by glen english
the SFDR is still 60dB. So you can improve dynamic range, but
not the
Post by Stuart Longland
Post by David Rowe
Post by glen english
SFDR. The SFDR, or more likely, where the third order two tone
intermods
Post by Stuart Longland
Post by David Rowe
Post by glen english
are, won't change. Some LT converters have incredibly good
SFDRs via
Post by Stuart Longland
Post by David Rowe
Post by glen english
internal digital dithering (later subtracted out in your
receiver) .
Post by Stuart Longland
Post by David Rowe
Post by glen english
For my commercial SDR, I use a 12 bit converter at 200 Msps.
The SFDR is 96dB, approx.
The converter input FSD is abotu +12dBm, so the IMD will be
always 12-96
Post by Stuart Longland
Post by David Rowe
Post by glen english
= -84dBm
so if I want my IMD down at -120dBm, then I need 36dB gain in
front of
Post by Stuart Longland
Post by David Rowe
Post by glen english
the receiver.
With such a high OSR (200M/ 10k)=43dB , the SNR is off in the
stratosphere, but the IMD dominates....
In my experience the SFDR is what will limit the sensitivity.
Watch out for ALIASED noise also. don't forget your converter
is also
Post by Stuart Longland
Post by David Rowe
Post by glen english
equally (almost) bringing in noise form 2fs, 3fs 4fs etc. SO
important
Post by Stuart Longland
Post by David Rowe
Post by glen english
that the convertor is seeing a low pass (nyquist) or band pass
filter
Post by Stuart Longland
Post by David Rowe
Post by glen english
(super nyquist sampling)
NOW what you can do is vary the voltage that the converter sees by
fiddlign with the termination and the nosie figure can be usefully
manipulated +/- 12dB (improved at the expense of full scale level)
The noise figure of the converter is approx (the input level -
the SNR)
Post by Stuart Longland
Post by David Rowe
Post by glen english
- 174
IE +12dBm FSD, SNR = 70, noise floor = -58dBm.
Now, that is for a 200 Msps, or 100 Msps nyquist bandwidth, that is
10log10(1e8) or 80dB
so -58 - 80 = -138dBm dBcHzSNR or 174 - 138 = 36dB.
cheers
Post by David Rowe
Hello Glen/Matt,
I'm working on a VHF radio prototype for testing some of my
open source
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
DV ideas. Could you pls explain how to work out the gain
required in
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC
with a 3Vpp
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the
minimum
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
signal would hit full scale on the ADC. Perhaps we could
scale that
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
back by 60dB plus some margin such that the MDS is still a few
dB above
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked
example would help.
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
Anyone else on the list with receiver design skills, pls feel
free to
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
comment. If a good reference exists I'm happy to dig that up.
Thanks,
David
------------------------------------------------------------------------------
Post by Stuart Longland
Post by David Rowe
Post by glen english
Post by David Rowe
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Post by David Rowe
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Stephen Hicks, N5AC
2015-10-28 13:26:52 UTC
Permalink
​David,

What you're asking is not a simple question. It is the bulk of the work to
make a good receiver -- figuring out the answers to these questions and
making the decisions about how your design will perform. I recommend
reading everything you can get your hands on from TI and Analog Devices​
that talk about design with an ADC. I can't tell for sure if you are
looking at a wide-band design or a narrow one, but it looks like
wide-band. Here's a good paper to get started that works out NF in an ADC,
but there are many more:

http://www.ti.com/lit/an/slyt090/slyt090.pdf

A couple of points:
1. SFDR from the manufacturer is based on the assumption that you will be
looking at (demodulating) large swaths of the spectrum and that you are
concerned about having a spur anywhere in that reception bandwidth. It
also assumes that you will generally pick a converter and then want to
receive everything in the first Nyquist zone. For example, the data sheet
assumes you will pick a 125Msps converter, place your Nyquist frequency at
62.5MHz and then want to simultaneously receive everything from 0-62.5MHz
(less filter skirts). As hams, this is not what we do so the requirements
change. Your selection of the sampling frequency will largely place many
of the larger spurs that contribute to SFDR and if you are receiving a
narrow bandwidth, you can place spurs where you want them, effectively
raising the SFDR. In other words, selection of sampling frequency, itself,
can be very important.

2. You can make a number of significant trade-offs in receiver design that
are not win-win. You must look at each decision and decide which is best
for your application. Is noise figure or intermodulation performance most
important in your design? Do your customers need a 1dB noise figure or is
10dB fine? In the VHF world, will your customers be "real VHFers" that put
a preamp on the tower or will they expect you to have an amazing noise
figure and sacrifice other parameters? If overload a concern or are you
willing to sacrifice some overload performance to decrease noise figure?

​Very few hams really understand how to work out the answers to the
questions you are asking. Ultimately when you have a design on a PCB, you
will really want to understand the questions you're asking and your
predicted answers. Then you can test what you've learned against your
receiver. In my opinion, there are no shortcuts to reading everything you
can get your hands on and asking lots of questions, being careful to
validate everything you hear against everything you read.

​Steve​
Post by David Rowe
I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?
For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.
Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.
I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.
Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.
Stephen Hicks, N5AC
VP Engineering
FlexRadio Systems™
4616 W Howard Ln Ste 1-150
Austin, TX 78728
Phone: 512-535-4713 x205
Email: ***@flexradio.com
Web: www.flexradio.com
Click Here for PGP Public Key
<https://sites.google.com/a/flex-radio.com/pgp-public-keys/n5ac>



*Tune In Excitement™*
PowerSDR™ is a trademark of FlexRadio Systems
Stuart Longland
2015-11-21 01:24:15 UTC
Permalink
Post by Stuart Longland
Post by David Rowe
2/ FB on taking a look at 700B mode. I described some suggested first
Post by David Rowe
steps on an email to the list on 24 Sep. Happy to work with you based
on the results of these unit tests. I imagine I'll be up for some modem
memory/CPU optimisation.
Yep, I did see that. I'm looking around for a suitable debugger board,
as it's impossible to see what's going on right now. All I have is some
STM32F103 boards (Cortex M3; 64kB RAM, 512kB flash, no FPU) and the
SM1000 which has no JTAG exposed.
The STLink/V2 programmer cables are not expensive and OpenOCD supports
them. Might be time to let some moths out of the wallet. ;-)
Well, I've just done that.

On order is a STM32F4-Discovery board (I was tossing up between it and
the STM32F411 board), a STLink/V2 (I know the discovery board has one
too) and a Lattice iCE40HX-8K FPGA break-out board.

That should be sufficient to let me "peer in" to what the SM1000 is up
to, as well as facilitating a bit more experimentation.
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
glen english
2015-11-21 22:17:54 UTC
Permalink
Stuart, SM1000 has the SWD pins (2 signals) exposed, doesn't it ?

use that.
Post by Stuart Longland
Post by Stuart Longland
Post by David Rowe
2/ FB on taking a look at 700B mode. I described some suggested first
Post by David Rowe
steps on an email to the list on 24 Sep. Happy to work with you based
on the results of these unit tests. I imagine I'll be up for some modem
memory/CPU optimisation.
Yep, I did see that. I'm looking around for a suitable debugger board,
as it's impossible to see what's going on right now. All I have is some
STM32F103 boards (Cortex M3; 64kB RAM, 512kB flash, no FPU) and the
SM1000 which has no JTAG exposed.
The STLink/V2 programmer cables are not expensive and OpenOCD supports
them. Might be time to let some moths out of the wallet. ;-)
Well, I've just done that.
On order is a STM32F4-Discovery board (I was tossing up between it and
the STM32F411 board), a STLink/V2 (I know the discovery board has one
too) and a Lattice iCE40HX-8K FPGA break-out board.
That should be sufficient to let me "peer in" to what the SM1000 is up
to, as well as facilitating a bit more experimentation.
--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
Stuart Longland
2015-11-22 08:07:11 UTC
Permalink
Post by glen english
Stuart, SM1000 has the SWD pins (2 signals) exposed, doesn't it ?
use that.
I would, but I don't have anything (yet) that will plug into SWD pins.
Only a Olimex JTag dongle.

This is something I hope Mouser will help me with later this week.
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
glen english
2015-11-22 08:32:03 UTC
Permalink
element 14 have STLINKV2s for $30
Post by Stuart Longland
Post by glen english
Stuart, SM1000 has the SWD pins (2 signals) exposed, doesn't it ?
use that.
I would, but I don't have anything (yet) that will plug into SWD pins.
Only a Olimex JTag dongle.
This is something I hope Mouser will help me with later this week.
--
-
Glen English
RF Communications and Electronics Engineer

CORTEX RF
&
Pacific Media Technologies Pty Ltd

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077



------------------------------------------------------------------------------
Steve
2015-10-25 00:49:58 UTC
Permalink
Added to the language in C99 if I remember right... No problem in GCC.

On Sat, Oct 24, 2015 at 7:01 PM, Stuart Longland
Post by Stuart Longland
Interestingly, we seem to be passing an integer non-const variable in
the declaration of these arrays; didn't think that was allowed.
------------------------------------------------------------------------------
Stuart Longland
2015-10-25 00:55:58 UTC
Permalink
Post by Steve
Added to the language in C99 if I remember right... No problem in GCC.
Ahh, figured it was a newer feature. I sometimes have to deal with K&R C.
--
Stuart Longland (aka Redhatter, VK4MSL)

I haven't lost my mind...
...it's backed up on a tape somewhere.

------------------------------------------------------------------------------
Steve
2015-10-25 01:30:41 UTC
Permalink
On Sat, Oct 24, 2015 at 7:55 PM, Stuart Longland
Post by Stuart Longland
Post by Steve
Added to the language in C99 if I remember right... No problem in GCC.
Ahh, figured it was a newer feature. I sometimes have to deal with K&R C.
The difference of course, is that Variable Length Arrays (VLA) are
allocated on the stack, rather than the heap, as in the old days.
Stack space may need to be weighed if you are creating some huge
arrays.

I'm kind of old fashioned in my C programming. I don't really like
HEAP or STACK, and tend to favor BSS. The nice thing about BSS
storage, is it is auto-initialized to zero. This can save a lot of
code at the initialization step, with loops allocating zero's to
arrays. Then to, there is no danger of the BSS crashing into the STACK
or the HEAP, while the later crash all the time out in the wild.

Somewhere along the line someone declared BSS evil (globals are evil)
and usage waned. Course now in OOP languages it is like making the
sign of the cross inside a Mosque...

Having looked at the cohpsk modem, it is going to need a ton of
memory, then too, you'll need to save room for the vocoder.

I think the best bet may be to load the two modems from flash
separately depending on which modem the user wants. Running both
probably will run out of memory. The cohpsk modem, for example doesn't
need all the pilot code and allocated space, but does have some rather
large filter tables.

Just some thinking out loud...

------------------------------------------------------------------------------
David Rowe
2015-10-25 02:23:44 UTC
Permalink
Hi Steve,

There's plenty of flash left for the cohpsk modem, we already have the
entire codec and fdmdv modem fitting in around half the flash.

No need to load any program code - it all runs out of flash.

It's important to test and characterise, hence the porting steps I
suggested on 24 Sep.

- David
Post by Steve
On Sat, Oct 24, 2015 at 7:55 PM, Stuart Longland
Post by Stuart Longland
Post by Steve
Added to the language in C99 if I remember right... No problem in GCC.
Ahh, figured it was a newer feature. I sometimes have to deal with K&R C.
The difference of course, is that Variable Length Arrays (VLA) are
allocated on the stack, rather than the heap, as in the old days.
Stack space may need to be weighed if you are creating some huge
arrays.
I'm kind of old fashioned in my C programming. I don't really like
HEAP or STACK, and tend to favor BSS. The nice thing about BSS
storage, is it is auto-initialized to zero. This can save a lot of
code at the initialization step, with loops allocating zero's to
arrays. Then to, there is no danger of the BSS crashing into the STACK
or the HEAP, while the later crash all the time out in the wild.
Somewhere along the line someone declared BSS evil (globals are evil)
and usage waned. Course now in OOP languages it is like making the
sign of the cross inside a Mosque...
Having looked at the cohpsk modem, it is going to need a ton of
memory, then too, you'll need to save room for the vocoder.
I think the best bet may be to load the two modems from flash
separately depending on which modem the user wants. Running both
probably will run out of memory. The cohpsk modem, for example doesn't
need all the pilot code and allocated space, but does have some rather
large filter tables.
Just some thinking out loud...
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
Steve
2015-10-25 02:31:29 UTC
Permalink
How are you doing on RAM space?
Post by David Rowe
Hi Steve,
There's plenty of flash left for the cohpsk modem, we already have the
entire codec and fdmdv modem fitting in around half the flash.
No need to load any program code - it all runs out of flash.
It's important to test and characterise, hence the porting steps I
suggested on 24 Sep.
- David
Post by Steve
On Sat, Oct 24, 2015 at 7:55 PM, Stuart Longland
Post by Stuart Longland
Post by Steve
Added to the language in C99 if I remember right... No problem in GCC.
Ahh, figured it was a newer feature. I sometimes have to deal with K&R C.
The difference of course, is that Variable Length Arrays (VLA) are
allocated on the stack, rather than the heap, as in the old days.
Stack space may need to be weighed if you are creating some huge
arrays.
I'm kind of old fashioned in my C programming. I don't really like
HEAP or STACK, and tend to favor BSS. The nice thing about BSS
storage, is it is auto-initialized to zero. This can save a lot of
code at the initialization step, with loops allocating zero's to
arrays. Then to, there is no danger of the BSS crashing into the STACK
or the HEAP, while the later crash all the time out in the wild.
Somewhere along the line someone declared BSS evil (globals are evil)
and usage waned. Course now in OOP languages it is like making the
sign of the cross inside a Mosque...
Having looked at the cohpsk modem, it is going to need a ton of
memory, then too, you'll need to save room for the vocoder.
I think the best bet may be to load the two modems from flash
separately depending on which modem the user wants. Running both
probably will run out of memory. The cohpsk modem, for example doesn't
need all the pilot code and allocated space, but does have some rather
large filter tables.
Just some thinking out loud...
------------------------------------------------------------------------------
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Helmut
2015-10-27 22:32:44 UTC
Permalink
Sorry for a typo: I mean the typical noise figure (NF) of ADCs is approx. 50
dB

73, Helmut

-----Ursprüngliche Nachricht-----
Von: Helmut [mailto:***@gmx.de]
Gesendet: Dienstag, 27. Oktober 2015 23:23
An: freetel-***@lists.sourceforge.net
Betreff: Re: [Freetel-codec2] gain before ADC

Hi David,

just my 2 cts. You will find in each datasheet of ADCs for RF apps the
typical parameters SNR, SFDR, ENOB, max. sampling rate and bandwidth. The
knowledge of these values, mostly relating to full scale and the Nyquist
bandwidth, are sufficient to define a frontend including the necessary
preamp, filtering and matching ADC to 50 ohms 'function blocks'. Together
with your channel bandwidth you can provide a reliable estimation of MDS and
dynamic range of the radio (my favorite direct sampling technique assumed,
hi). It's good choice to calculate with a figure of about 50 dB for the ADC.

Walt Kester of AD wrote a couple of nice tutorials, e.g.
http://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: David Rowe [mailto:***@rowetel.com]
Gesendet: Dienstag, 27. Oktober 2015 20:47
An: freetel-***@lists.sourceforge.net
Betreff: [Freetel-codec2] gain before ADC

Hello Glen/Matt,

I'm working on a VHF radio prototype for testing some of my open source
DV ideas. Could you pls explain how to work out the gain required in
front of my ADC?

For example if I have a MDS of -120dBm (0.224uV), and an ADC with a 3Vpp
(1.06Vrms) clipping point, and SFDR of say 60dB.

Is the gain rqd simply Av=1.06/0.224E-16? That would mean the minimum
signal would hit full scale on the ADC. Perhaps we could scale that
back by 60dB plus some margin such that the MDS is still a few dB above
the floor of the ADC.

I'm a bit mixed up by the idea of NF and ADCs. A worked example would help.

Anyone else on the list with receiver design skills, pls feel free to
comment. If a good reference exists I'm happy to dig that up.

Thanks,

David

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Helmut
2015-10-29 07:16:57 UTC
Permalink
Ups,....seems I got a problem also with to less coffee....

BPF insertion loss refers to pass band not stop band, hi.

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: Helmut [mailto:***@gmx.de]
Gesendet: Mittwoch, 28. Oktober 2015 23:29
An: freetel-***@lists.sourceforge.net
Betreff: Re: [Freetel-codec2] gain before ADC

Hi David,

I understood what you plan, but analogue down conversion is another story.
The example I sent you should demonstrate how this attached system
calculation tool works. It shows a VHF frontend for digital down conversion,
i.e. the ADC has to be sampled with 300 Msps. The BPF of 144 to 146 MHz
exhibits an insertion loss of 2 dB in the stop band and consequently a noise
figure of 2 dB.
In your case NF or MDS is mainly not determined by the ADC in the base band,
but on all analogue stages in front. It depends e.g. on what kind of mixer
you intend to use: balanced passive mixers exhibit an insertion loss of 7-8
dB (equal NF 7- 8 dB), while modern active mixer provide even conversion
gain. BTW negative NF doesn’t exist. I guess you meant negative gain (loss)
of the BPF.
Nevertheless you can use that SYScal tool of course also for your approach
to calculate the necessary gain of preamp and IF amp.


73, Helmut, DC6NY





------------------------------------------------------------------------------
Helmut
2015-10-29 08:32:33 UTC
Permalink
Hello David,

another hint: If the dynamic range is not so important and for system tests
you can use one of these RTL28xx chips providing 8-Bit I,Q samples for
direct access or a complete VHF/UHF-RX. See
http://sdr.osmocom.org/trac/wiki/rtl-sdr

73, Helmut, DC6NY


-----Ursprüngliche Nachricht-----
Von: Helmut [mailto:***@gmx.de]
Gesendet: Donnerstag, 29. Oktober 2015 08:17
An: freetel-***@lists.sourceforge.net
Betreff: [Freetel-codec2] WG: gain before ADC

Ups,....seems I got a problem also with to less coffee....

BPF insertion loss refers to pass band not stop band, hi.

73, Helmut, DC6NY

-----Ursprüngliche Nachricht-----
Von: Helmut [mailto:***@gmx.de]
Gesendet: Mittwoch, 28. Oktober 2015 23:29
An: freetel-***@lists.sourceforge.net
Betreff: Re: [Freetel-codec2] gain before ADC

Hi David,

I understood what you plan, but analogue down conversion is another story.
The example I sent you should demonstrate how this attached system
calculation tool works. It shows a VHF frontend for digital down conversion,
i.e. the ADC has to be sampled with 300 Msps. The BPF of 144 to 146 MHz
exhibits an insertion loss of 2 dB in the stop band and consequently a noise
figure of 2 dB.
In your case NF or MDS is mainly not determined by the ADC in the base band,
but on all analogue stages in front. It depends e.g. on what kind of mixer
you intend to use: balanced passive mixers exhibit an insertion loss of 7-8
dB (equal NF 7- 8 dB), while modern active mixer provide even conversion
gain. BTW negative NF doesn’t exist. I guess you meant negative gain (loss)
of the BPF.
Nevertheless you can use that SYScal tool of course also for your approach
to calculate the necessary gain of preamp and IF amp.


73, Helmut, DC6NY





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